For a more advanced example check out Thomas' MyHDL/eispice Mixed-Mode Example.

capacitor.py

import eispice
cct = eispice.Circuit("Capacitor Test")
cct.Vx = eispice.V(1, eispice.GND, 4,
  eispice.Pulse(4, 8, '10n', '2n', '3n', '5n', '20n'))
cct.Cx = eispice.C(1, eispice.GND, '10n')
cct.tran('0.5n', '100n')
eispice.plot(cct)

current_pulse.py

import eispice
cct = eispice.Circuit("Current Pulse Test")
cct.Ix = eispice.I(1, eispice.GND, 4,
  eispice.Pulse(4, 8, '10n', '2n', '3n', '5n', '20n'))
cct.Vx = eispice.V(2, 1, 0)
cct.Rx = eispice.R(2, eispice.GND, 10)
cct.tran('0.5n', '100n')
eispice.plot(cct)

ibis.py

import eispice
ibs = eispice.Ibis('test')
cct = eispice.Circuit('IBIS Test')
cct.Driver = ibs['2']('vs')
cct.Rt = eispice.R('vs', 'vi', 33.2)
cct.Tg = eispice.T('vi', 0, 'vo', 0, 50, '2n')
cct.Receiver = ibs['1']('vo')
cct.tran('0.01n', '20n')
eispice.plot(cct)

nonlinear_c.py

import eispice
cct = eispice.Circuit("Non-Linear Capacitor Test")
wave = eispice.Pulse('1u', '10u', '10n', '5n', '3n', '5n', '50n')
cct.Vc = eispice.V(3, 0, '1n', wave)
cct.Vx = eispice.V(1, 0, 1,
  eispice.Pulse('1m', '10m', '10n', '2n', '3n', '5n', '20n'))
cct.Cx = eispice.BC(1, 0, 'v(3)*10')
cct.tran('0.5n', '100n')
eispice.plot(cct)

nonlinear_i.py

import eispice
cct = eispice.Circuit("Nonlinear Current Test")
cct.Rv = eispice.R(1, eispice.GND, 10)
cct.Vx = eispice.V(1, eispice.GND, 7)
cct.Rb = eispice.R(2, eispice.GND, 3)
cct.Bx = eispice.B(2, eispice.GND, eispice.Current,
  "4.739057e-04 * (uramp( v(2,0) --5.060000e+00)) + sqrt(v(1)) / sinh(i(Vx))")
cct.op()
cct.check(1, 7)
cct.check(2, 10.44121563)
cct.check('Vx', -0.7, eispice.Current)

nonlinear_time.py

import eispice
cct = eispice.Circuit("Nonlinear Time Test")
cct.Rb = eispice.R(2, eispice.GND, 3)
cct.Bx = eispice.B(2, eispice.GND, eispice.Voltage, 'sin(2*3.14159*100e6*time)')
cct.tran('0.5n', '15n')
eispice.plot(cct)

pyb_fets.py

import eispice
cct = eispice.Circuit('PyB Defined Behavioral MOS Divider Test')
class PMOS(eispice.PyB):
  def __init__(self, d, g, s, k=2.0e-6, w=2, l=1, power=2.0):
    eispice.PyB.__init__(self, d, s, eispice.Current, self.v(g), self.v(s))
    self.Vt = 0.7
    self.beta = k * (w/l)
    self.power = power
  def model(self, Vg, Vs):
    if ((Vs - Vg) > self.Vt):
      return -0.5* self.beta * (Vs - Vg - self.Vt)**self.power
    else:
      return 0.0
class NMOS(eispice.PyB):
  def __init__(self, d, g, s, k=5.0e-6, w=2, l=1, power=2.0):
    eispice.PyB.__init__(self, d, s, eispice.Current, self.v(g), self.v(s))
    self.Vt = 0.7
    self.beta = k * (w/l)
    self.power = power
  def model(self, Vg, Vs):
    if ((Vg - Vs) > self.Vt):
      return 0.5* self.beta * (Vg - Vs - self.Vt)**self.power
    else:
      return 0.0
    cct.Vcc = eispice.V('vcc', eispice.GND, 3.3)
    cct.Mx = PMOS('vg', 'vg', 'vcc', k=2.0e-6)
    cct.My = NMOS('vg', 'vg', eispice.GND, k=5.0e-6)
    cct.Rl = eispice.R('vg', eispice.GND, '10G')
    cct.op()
    cct.check('vg', 1.436097)

subckt.py

import eispice
class Subckt1(eispice.Subckt):
  def __init__(self, pNode, nNode, Rx, Ry):
    self.Rx = eispice.R(pNode, self.node('node'), Rx)
    self.Ry = eispice.R(nNode, self.node('node'), Ry)
class Subckt2(eispice.Subckt):
  def __init__(self, pNode, nNode, Rx, Ry):
    self.Rx = eispice.R(pNode, self.node('node'), Rx)
    self.Xy = Subckt1(nNode, self.node('node'), Rx, Ry)
cct = eispice.Circuit("Subckt Test")
cct.Vx = eispice.V(1, 0, 10)
cct.Xx = Subckt2(1, 0, 100, 100)
cct.op()
cct.check('Vx', -10.0 / 300.0, eispice.Current)

tline.py

import eispice
cct = eispice.Circuit("Simple Transmission Line Model Test")
wave = eispice.Pulse(0, 1, '15n', '1n', '1n', '15n', '100n')
cct.Vs = eispice.V('vs', eispice.GND, 0, wave)
cct.Rs = eispice.R('vs', 'vi', 30)
cct.Tg = eispice.T('vi', eispice.GND, 'vo', eispice.GND, 50, '5n', 0.5)
cct.Rl = eispice.R('vo', eispice.GND, '10k')
cct.Cl = eispice.C('vo', eispice.GND, '5p')
cct.tran('0.1n', '200n')
eispice.plot(cct)